Dynamic Random Access (DRAM) memory is a widely used type of memory. An important characteristic of DRAM memories is that data stored in a DRAM must be periodically refreshed, if not the data will be lost.
External access requests for data generally come at random times. Thus, an external access and a refresh access request can possibly be initiated at the same time. In some memory systems, access to a DRAM is postponed while a refresh operation is taking place. Such systems have variable latencies, thereby increasing the complexity of the system and consuming increased memory bandwidth. In other systems, the cycle timing is designed so that both an external access and a refresh can occur within the allowable cycle time. This prevents the refresh operation from interfering with an external access request.
The time required to access data stored in a memory is termed the access time of the memory. It is well known, that a high speed, static random access memory (SRAM) cache can be added to a memory system in order to decrease average access time. Recently used data is stored in the high speed cache so that many times, a read request can be satisfied without accessing the slower speed main memory. The cache hit rate is a measure of the percentage of times that desired data is in the cache thereby avoiding the necessity of accessing the main memory to fulfill an access request. The actual access time for a memory system is dependent upon the cache hit rate.
The present invention is directed to a method and system for accessing a DRAM memory where the refresh cycle does not generally delay access to the memory.